1. Field of the Invention
The present invention relates to semiconductor integrated circuits (ICs) and particularly to an improvement in a pattern layout and a conductor structure of a semiconductor IC.
2. Description of the Background Art
FIG. 1A is a schematic top view showing an example of a pattern layout of a conventional semiconductor IC and FIG. 1B is a schematic sectional view taken along the line 1B--1B in FIG. 1A. Referring to those figures, a semiconductor chip 101 comprises circuit blocks 1a to 1f. Each of those circuit blocks is formed in an epitaxial N layer 103 on a P.sup.- semiconductor substrate 102 and surrounded by P.sup.+ isolation regions 104. The epitaxial layer 103 is covered with an oxide film 105. Ground lines 106 penetrate the oxide film 105 and they are in ohmic contact with the P.sup.+ isolation regions 104, whereby potentials of the P.sup.+ isolation regions 104 and P.sup.- substrate 102 are stably set to a ground potential.
A bundle of ground lines 106 extend from a ground bonding pad GND provided on the left of the semiconductor chip 101 through a central region of the semiconductor chip 101 and the ground lines 106 are distributed from the bundle to the corresponding circuit blocks 1a to 1f. Power supply lines extend from a power supply bonding pad Vcc provided on the right of the semiconductor chip 101 to peripheral regions of the semiconductor chip 101 so that they are connected to the corresponding circuit blocks.
In general, signals processed in the circuit blocks 1a to 1f have different frequencies and amplitude levels and those circuit blocks 1a to 1f have different functions. Thus, the circuit blocks 1a to 1f have different numbers of circuit elements and they have different areas. Accordingly, it is not easy to arrange efficiently the circuit blocks 1a to 1f having different areas in a small area. In addition, if the circuit block 1a for example is replaced by a modified circuit block (having a different area from the circuit block 1a) or a new circuit block is added, it is often necessary to rearrange all the circuit blocks 1a to 1f in order to set such a modified or new circuit block efficiently in a reduced area.
Further, in the case of arranging the circuit blocks, it is desirable to reduce the total area occupied by those circuit blocks and at the same time it is necessary to take measures to minimize undesirable mutual interferences of the circuit blocks. Consequently, for example in the case of changing part of a certain IC device in compliance with a request of a user, it is often necessary to entirely change the design of the circuit block pattern, which takes time and involves considerable cost.
Further, inter-block lines 108 such as signal lines or feedback lines between the circuit blocks might be subjected to interference due to undesirable radiation from the circuit blocks which process high-frequency signals. The inter-block lines 108 are only shown between the circuit blocks 1a and 1b in FIG. 1A for the purpose of simplification of the drawing.
In addition, it is necessary to take account of three-dimensional crossing between the inter-block lines 108, the power supply lines 107 and the ground lines 106, causing the design of the conductor pattern to be complicated.